Moazez, Mahsa and Safaei, Farshad and Rezazadeh, Majid (2023) Design and implementation of multistage interconnection networks for SoC networks. International journal of computer science, engineering and information technology (IJCSEIT), 13 (5). pp. 1-11. ISSN 2231-3117

- Published Version Restricted to Registered users only Volltext (307Kb)

Abstract

In this paper the focus is on a family of Interconnection Networks (INs) known as Multistage Interconnection Networks (MINs). When it is exploited in Network-on-Chip (NoC) architecture designs, smaller circuit area, lower power consumption, less junctions and broader bandwidth can be achieved. Each MIN can be considered as an alternative for an NoC architecture design for its simple topology and easy scalability with low degree. This paper includes two major contributions. First, it compares the performance of seven prominent MINs (i.e. Omega, Butterfly, Flattened Butterfly, Flattened Baseline, Generalized Cube, Beneš and Clos networks) based on 45nm-CMOS technology and under different types of Synthetic and Trace-driven workloads. Second, a network called Meta-Flattened Network (MFN), was introduced that can decrease the blocking probability by means of reduction the number of hops and increase the intermediate paths between stages. This is also led into significant decrease in power consumption.

Item Type:	Article
Uncontrolled Keywords:	System on Chip (SoC), Multistage Interconnection Network (MIN), Performance Evaluation, Flattened Butterfly
Subjects:	Generalities, computers, information > Computer science, internet
Divisions:	School of Computing Science, Business Administration, Economics and Law > Department of Computing Science
Date Deposited:	16 Apr 2024 10:20
Last Modified:	16 Apr 2024 10:20
URI:	https://oops.uni-oldenburg.de/id/eprint/6309
URN:	urn:nbn:de:gbv:715-oops-63908
DOI:	10.48550/arXiv.1212.0310
Nutzungslizenz:

Actions (login required)

View Item